Espressif Systems /ESP32-S3 /I2C0 /FIFO_CONF

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Interpret as FIFO_CONF

Description

FIFO configuration register.

Fields

RXFIFO_WM_THRHD	The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid.
TXFIFO_WM_THRHD	The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid.
NONFIFO_EN	Set this bit to enable APB nonfifo access.
FIFO_ADDR_CFG_EN	When this bit is set to 1, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM.
RX_FIFO_RST	Set this bit to reset rx-fifo.
TX_FIFO_RST	Set this bit to reset tx-fifo.
FIFO_PRT_EN	The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty.

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